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NIELIT Recruitment 2026 – VLSI Design Expert & Junior VLSI Engineer Walk‑In

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NIELIT Recruitment 2026 – VLSI Design Expert & Junior VLSI Engineer Walk‑In | PRESENT RESULT

NIELIT Recruitment 2026 – Walk‑in for VLSI Design Expert & Junior VLSI Engineer Posts

The National Institute of Electronics & Information Technology (NIELIT) has issued an official recruitment notification for the year 2026 inviting eligible candidates to attend a walk‑in interview for the posts of VLSI Design Expert and Junior VLSI Engineer. This recruitment is under Advt. No. NIELIT/NOIDA/CoE/2026/04 and the walk‑in interview is scheduled to take place on 25‑02‑2026 at the NIELIT Centre of Excellence in Chip Design, Noida. Candidates with a Master’s degree or Bachelor’s degree with relevant experience in Electronics & Communication, Electrical Engineering, or VLSI Design are eligible to attend the interview.

The recruitment is purely on a contract basis with a consolidated salary, and interested candidates should appear in person for the interview along with all necessary documents. This page provides complete details about vacancies, eligibility criteria, important dates, selection process, application fee, and official links to download the notification and application form.

Please read the entire notification carefully before attending the walk‑in interview. All details below are based on the official announcement and verified information.

Recruitment Overview

Organization National Institute of Electronics & Information Technology (NIELIT)
Posts VLSI Design Expert & Junior VLSI Engineer
Advertisement No. NIELIT/NOIDA/CoE/2026/04
Total Vacancies 02 Posts
Application Mode Walk‑In Interview
Official Website nielit.gov.in

Important Dates

Event Date
Walk‑in Interview & Document Verification 25‑02‑2026

Application Fee

Category Application Fee
General / OBC / EWS ₹500/‑ (Non‑Refundable)
SC / ST / PwD / Women ₹500/‑ (Non‑Refundable)

Age Limit

Criteria Details
Maximum Age Up to 45 Years
Age As On 25‑02‑2026

Eligibility Criteria

  • Master’s degree in Electronics & Communication, Electrical Engineering, VLSI Design, or related field from a recognized University/Institute.
  • OR Bachelor’s degree in Electronics & Communication, Electrical Engineering, VLSI Design, or related field with minimum two years of relevant experience.
  • Candidates must carry all original certificates and relevant documents to the interview venue.
  • Experience in VLSI design or related projects is desirable for the Junior VLSI Engineer post.

Selection Process

  • Document Verification at the interview venue.
  • Personal Walk‑in Interview.

Salary & Benefits

Post Consolidated Salary
VLSI Design Expert / Junior VLSI Engineer ₹40,000/‑ per month

How to Attend Walk‑In Interview

  1. Visit the official NIELIT recruitment page: nielit.gov.in/recruitments
  2. Read the official notification NIELIT/NOIDA/CoE/2026/04 carefully.
  3. Prepare all original documents including educational certificates, experience proof, identity proof, and photographs.
  4. Reach the interview venue on 25‑02‑2026 with all documents.
  5. Attend document verification and interview as per schedule.

Important Links

Link Name URL
Official Recruitment Notification nielit.gov.in/recruitments
Official Website nielit.gov.in
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